Data is stored on magnetic tape in one or more parallel tracks, each track including a series of fixed magnetization areas between which areas occur magnetic flux transitions. Each track can be divided into discreet segments or "bit cells" wherein a magnetic flux transition may or may not occur.
The occurrence or non-occurrence of a flux transition within a cell is converted into binary electronic data via any one of a number of codes provided therefore. For example, with non-return-to-zero input (NRZI) encoding, a flux transition within a bit cell causes a switching from one of two discrete voltage levels (e.g., high and low) to the other, indicating a logical "one". The non-occurrence of a transition within a bit cell results in no switching, indicating a logical "zero". Another example of the "double frequency" code which causes a switching coincident with a logical one, between consecutive zeros, and between each one and zero, but not between two consecutive ones.
Efforts to increase the speed at which data can be placed in storage, retrieved and transmitted, has led to increased data density, i.e., more bit cells per unit length of tape. The increased bit density or bit crowding can cause bit shift, or the reading of magnetic flux transition off-center within their respective bit cells or even outside the cells. The effect of bit shift can be a phase drift or loss of synchronization between an incoming data signal and a clock signal. Further synchronization difficulties arise from mechanical speed variations or in "fishtailing" of the tape. As data density is increased, the problems become more pronounced. One approach to reducing phase drift is group code recording (GCR) or run-length-limited coding, wherein the number of consecutive zeros is limited. For example, U.S. Pat. No. 3,566,351 to Sekse et al granted Feb. 23, 1971 discloses a data transmission system in which each switching between zero and one resynchronizes a receiving oscillator to a transmitting oscillator. To avoid excessive drift between oscillators, characters are written in a code permitting in each character a maximum of two consecutive zeros or ones, insuring that a data word will contain at most four consecutive zeros or ones. U.S. Pat. No. 3,852,687 to Hodges granted Dec. 3, 1974 shows an improvement of the modified frequency modulation (MFM) method whereby the number of clock periods for an eight bit byte is reduced from 16 to 13, thereby increasing density of data for a given magnetic switching density.
One known method of maintaining synchronization between incoming data signals and clock signals, despite some bit shift, is the use of a phase locked oscillator. A phase comparator determines the shift in phase between the input data signal and the output from a voltage controlled oscillator (VCO) used to drive a clock. Based on the phase difference between clock and data, a signal is generated to increase or decrease voltage to the VCO thereby tending to resynchronize the clock with the incoming signal. By combining the VCO with a frequency multiplier and including it in a phase locked loop with a counter dividing the frequency by the same number, e.g., 5, the maximum possible error can be reduced from pi radians to pi/5 radians. Such an improvement is shown in U.S. Pat. No. 4,005,479 to Hunnicutt, granted Jan. 25, 1977 and assigned to the assignee herein.
Disadvantages associated with the use of a voltage controlled oscillator included variations in frequency caused by temperature and component value drift. As frequency changes, the loop tends to unlock and may even oscillate or hunt around a new frequency. To avoid these disadvantages, U.S. Pat. No. 3,973,209 granted to Nossen et al on Aug. 3, 1976 discloses a closed loop which replaces the VCO with a variable register 13 and a fixed register 16. The value stored in fixed register 16 is representative of the nominal frequency, while the numbers stored in variable register 13 represent the Doppler or variation from the base or nominal frequency.
Another method for insuring synchronization of data is by provision of a synchronizing word or marker bit. In U.S. Pat. No. 3,576,947 to Kruger granted May 4, 1971, each 240 bit frame includes a sync word or its complement. By processing either the sync word or complement thorugh a shift register and aligning the sync word or complement from the adjoining frame, frames of different data streams can by synchronized. U.S. Pat. No. 3,789,400 to Towns granted Jan. 29, 1974 shows an apparatus for correcting the skewing of data caused by fishtailing of magnetic tape. Data recorded on separate tracks is led by a marker bit in each track. The marker bits are moved through a shift register to an "AND" gate. When the marker bits from all tracks reach the AND gate it is enabled so that data from all tracks are read simultaneously.